Virtual Memory:

                  A technique that uses main memory as a “cache” for secondary storage. Historically, there were two major motivations for virtual memory: to allow efficient and safe sharing of memory among multiple programs, and to remove the programming burdens of a small, limited amount of main memory. Four decades after its invention, it’s the former reason that reigns today.

Consider a collection of programs running at once on a computer. The total memory required by all the programs may be much larger than the amount of main memory available on the computer, but only a fraction of this memory is actively being used at any point in time. Main memory need contain only the active portions of the many programs, just as a cache contains only the active portion of one program. Thus, the principle of locality enables virtual memory as well as caches, and virtual memory allows us to efficiently share the processor as well as the main memory. Of course, to allow multiple programs to share the same memory, we must be able to protect the programs from each other, ensuring that a program can only read and write the portions of main memory that have been assigned to it.

We cannot know which programs will share the memory with other programs when we compile them. In fact, the programs sharing the memory change dynamically while the programs are running. Because of this dynamic interaction, we would like to compile each program into its own address space— separate range of memory locations accessible only to this program. Virtual memory implements the translation of a program’s address space to physical addresses. This translation process enforces protection of a program’s address space from other programs.

The second motivation for virtual memory is to allow a single user program to exceed the size of primary memory. Formerly, if a program became too large for memory, it was up to the programmer to make it fit. Programmers divided programs into pieces and then identified the pieces that were mutually exclusive. These overlays were loaded or unloaded under user program control during execution, with the programmer ensuring that the program never tried to access an overlay that was not loaded and that the overlays loaded never exceeded the total size of the memory. Overlays were traditionally organized as modules, each containing both code and data. Calls between procedures in different modules would lead to overlaying of one module with another. As you can well imagine, this responsibility was a substantial burden on programmers. Virtual memory, which was invented to relieve programmers of this difficulty, automatically manages the two levels of the memory hierarchy represented by main memory (sometimes called physical memory to distinguish it from virtual memory) and secondary storage.

Although the concepts at work in virtual memory and in caches are the same, their differing historical roots have led to the use of different terminology. A virtual memory block is called a page, and a virtual memory miss is called a page fault. With virtual memory, the processor produces a virtual address, which is translated by a combination of hardware and software to a physical address, which in turn can be used to access main memory. Figure below shows the virtually addressed memory with pages mapped to main memory. This process is called address mapping or address translation. Today, the two memory hierarchy levels controlled by virtual memory are DRAMs.

Physical address:  An address in main memory.

Protection: A set of mechanisms for ensuring that multiple processes sharing the processor, memory, or I/O devices cannot interfere, intentionally or unintentionally, with one another by reading or writing each other’s data. These mechanisms also isolate the operating system from a user process.

Page fault:  An event that occurs when an accessed page is not present in main memory.

Virtual address: An address that corresponds to a location in virtual space and is translated by address mapping to a physical address when memory is accessed.

Address translation: Also called address mapping. The process by which a virtual address is mapped to an address used to access memory.

In virtual memory, blocks of memory (called pages) are mapped from one set of addresses (called virtual addresses) to another set (called physical addresses).

ARM PROCESSOR MODES

The access rights of the processor mode are done in the Current Program Status Register (CPSR) itself. The processor mode is used to determine which registers are active. Each processor mode is either privileged mode or non privileged : A privileged mode allows the full read-write access to the CPSR. Conversely, A non privileged mode still allows read access to the control field in the CPSR but still allows read-write access to the conditional fields. 

There are seven processor modes in total. Out of which six are privileged modes and one is non privileged mode(user). The six privileged modes are Abort mode; Fast interrupt mode, Interrupt request mode, Supervisor mode, System mode, and Undefined mode. The processor enters the abort mode when there is a failed attempt to access memory. Fast interrupt request and Interrupt request modes correspond to the two interrupt levels available on the ARM processor. Supervisor mode is the mode that the processor   is in after the reset and is generally the mode that an operating system kernel operates in. System mode is a special version of user mode that allows full read-write access to the CPSR. Undefined mode is used when the processor encounters an instruction that is undefined or not supported by the implementation. User mode is used for programs and applications.

There are 37 registers in register file. Out of which, 20 registers are hidden from a program at different times. These registers are called banked registers.  These banked registers are available only when the processor, is in a particular mode. The registers of particular mode are denoted by an underline character post-fixed to the mode mnemonics or _mode. For example, banked registers r13_abt, r14_abt and spsr_abt are available only when the processor is in abort mode.

Every processor mode expect user mode can change mode by writing directly to the mode bits of the CPSR. All processor modes except system mode have a set of associated banked register that are a subset of the main 16 registers. A banked register maps one-to-one onto a user mode register. If the processor mode is changed, a banked register from the new mode will replace an existing register.

For example, when the processor is in the interrupt request mode, the instruction you execute still access registers named r13 and r14. However, these registers are the banked registers r13_irq and r14_irq. The user mode registers r13_usr and r14_usr are not affected by the instruction referencing these registers. A program still has normal access to other registers r0 to r12.

The processor mode can be changed by a program that writes directly to the CPSR only if the processor core has to be in privileged mode or by hardware when the core responds to an exception or interrupt.

ARM PROCESSOR FUNDAMENTAL

The arm core has functional units such as ALU, Address registers, Register file, Barrel shifter, MAC and instruction decoder. All these functional blocks are connected by data buses.

DATA enters the processor core through the data bus. The data may be an instruction to be executed or a data item. Basically, ARM core follows Von Neumann implementation of the ARM in which the data items and instructions share the same bus. In contrast, Harvard implementations of the ARM use two separate buses, one of the data items and other for the instructions.

Instruction decoder translates the instruction into the binary form (executable form) before they are executed. Each instruction executed belongs to a particular instruction set.

The ARM processor uses load-store architecture. This means it has two, instruction types for transferring data in and out of the processor.  They are LOAD and STORE.

LOAD instructions copy data from memory to register in the core, and conversely the STORE instruction copy data from register to memory. These are no data processing instructions that directly manipulate data in memory. Thus data processing is carried out solely in registers. Data items are placed in the register file called as storage bank made up of 32-bit registers. Since the ARM core is 32-bit processor, most instructions treat the registers as holding signed or unsigned 32-bit values. The sign extend hardware converts signed 8-bit and 16-bit numbers to 32-bit values as they read from memory and placed in a register.

ARM instruction typically have two source registers i.e, Rn and Rm, and a single result or destination register, Rd. Source operands are read from the register file using the internal buses A and B, respectively. The ALU (arithmetic logic unit) takes the register values Rn and Rm from the A and B buses and computes a result. Data processing instructions write the result in Rd directly to the register file. Load and Store instruction use the ALU to generate an address to be held in the address register and broadcast on the Address bus.

One important feature of the ARM is that register Rm alternatively can be p reprocessed in the barrel shifter before it enters the ALU. Together the Barrel shifter and ALU can calculate a wide range of expressions and address. After passing through the functional units, the result in Rd is written back to the register  file using the Result bus. For load and store instructions the increment-er updates the address register before the core reads or writes the next register value from or to the next sequential

Memory location .The processor continues executing instruction until an exception or interrupt changes the normal execution flow.   

CATEGORIES OF COMPUTER NETWORKS

Today when we speak of networks we are generally referring to three primary categories, local area networks, metropolitan area networks, and wide area networks. Into which category a network falls is determined by its size, its ownership, the distance it covers, and its physical architecture.

Local Area Network (LAN): A Local Area Network (LAN) is usually privately owned and pinks the devices in a single office, building, or campus. Depending on the needs of an organization and the type of technology used, a LAN can be as simple as two PC's and a printer in someone's home office; or it can be extend throughout a company and include audio and video peripherals. Currently LAN size is limited to few kilometers.

LAN's are designed to allow resources to be shared between personal computers or workstations. The resources to be shared can include hardware, software, or data. A common example of   a  LAN, found in many business environments, links a workgroup of task related computers, for example, engineering workstations or accounting PC. In addition to size, LAN's are distinguished from other types of networks by their transmission media and topology .The most common LAN topologies are bus, ring, and star.

Metropolitan-Area Network (MAN)  :  A metropolitan-area network (MAN) is designed to extend over an entire city. It may be a single network such as a cable television network, or it may be a means of connecting a number of LAN's into larger networks resources may be a means of connecting a number of LAN's into a larger networks so that resources may be shared by LAN- to - LAN as well as device to device. A MAN may be wholly owned and operated by a private company, or it may be a service provided by a public company, such as a local telephone company. Many telephone companies provide a popular MAN service called Switched Multi-megabit Data Services (SMDS)

Wide Area Network (WAN): A wide area network (WAN) provides long-distance transmission of data, voice, images, and video information over large geographic areas that may comprise a country, a continent, or even the whole world. In contrast to LANs, WANs may utilize public, leased, or private communication equipment, usually in combinations, and can therefore span an unlimited number of miles. A WAN that is wholly owned and used by a single company is often referred to as an enterprise network.

BASICS OF COMPUTER NETWORKS

Network:

A network is a set of devices (often referred as nodes) connected by communicating links. A node can be computer, printer, or any other devices capable of sending and receiving data generated by other nodes on the network.

Types of connection:

A link is a communications pathway that transfers data from one device to another. For visualization purpose, it is simplest to imagine any link as line drawn between two points. For communication to occur, two devices must be connected in some way to the same link at the same time. There are two possible types of connections,

• Point-to-point
• Multi-point

Point-to-point: A point-to-point connection provides a dedicated link between two devices. The entire capacity of the link is reserved for transmission between those two devices. Most point-to-point connections use an actual length of wire or cable to connect the two ends, but other options, such as microwave or satellite links, are also possible..

Multi-point: A multi-point (also called multi-drop) connection is one in which more than two specific devices share a single link. In a multi-point environment, the capacity of the channel is shared, either spatially or temporally. If several devices can use the link simultaneously, it is a spatially shared connection. If users must take turns, it is a timeshare connection.

Physical  topology :

The term physical topology refers to the way in which a network is laid out physically. Two or more devices connect to a link; two or more links form a topology. The topology of a network is the geometric representation of the relationship of all the links and linking devices (usually called nodes) to one another. There are four basic topology possible they are,

• Mesh
• Star
• Bus
• Ring

Mesh: In a mesh topology, every device has a dedicated point-to-point link to every other device. The term dedicated means that the link carries traffic only between the two devices it connects.  A mesh offers several advantages over other network topologies. First, the use of dedicated links guarantees that each connection can carry its own data load, thus eliminating the traffic problems that can occur when links must be shared by multiple devices. Second a mesh topology is robust. If one link becomes unusable, it does not incapacitate the entire system.

Star topology: In a star topology, each device has a dedicated point-to-point link only to a central controller, usually called a hub. The devices are not directly linked to one another. Unlike a mesh topology, a star topology doesn't allow direct traffic between devices. The controller acts as an exchange; if one device wants to send data to another, it sends the data to the controller, which then relays the data to other connected device. A star topology is less expensive than a mesh topology.

Bus topology: A bus topology is multi-point. One long cable acts as a backbone to link all the devices in a network. Nodes are connected to the bus cable by drop lines and traps. A drop line is a connection running between the device and the main cable. A tap is a connector that either splices into the main cable or punctures the sheathing of a cable to create a contact with metallic core. A bus uses less cabling than a mesh or star topologies.

Ring topology: In a ring topology, each device has a dedicated point-to-point connection only with the two devices on either side of it. A signal is passed along the ring in one direction, from device to device, until it reaches its destination. Each device in the ring incorporates a repeater. When a device receives a signal intended for another device, its repeater regenerates the bits and passes them along.

8051 MICROCONTROLLER

   Microcontroller is a single chip which has a central processing unit in addition RAM, ROM, TIMMERS, COUNTERS and INPUT/ OUTPUT Ports. In other words the central processing unit (Processor), RAM, ROM, TIMMERS, COUNTERS and INPUT/ OUTPUT Ports are all embedded together on one chip, therefore the designer cannot add any external memory, INPUT/ OUTPUT Ports or timers to it.

HISTORY OF 8051 MICROCONTROLLER: In 1981, Intel Corporation introduced an 8-bit microcontroller called the 8051.This microcontroller had 128 bytes of RAM, 4K bytes  of on-chip ROM, two timers one serial port , and four INPUT/ OUTPUT Ports each of 8 bits wide all on single chip. At the time it was also referred to as a “SYSTEM ON A CHIP”, the 8051 is an 8-bit processor, meaning that the central processing unit (CPU) can work on only on 8 bits of data at a time. Data larger than 8 bits has to be broke into 8-bit pieces to be processed by the central processing unit. The 8051 has 4 INPUT/ OUTPUT Ports, each of 8 bits wide. Although the 8051 can have maximum of 64K bytes of on-chip ROM, many manufacturers have put only 4K bytes on the chip.

CRITERIA TO CHOOSE A MICROCONTOLLER: The first and foremost criterion in choosing a microcontroller is that it must meet the task at hand efficiently and cost effectively.

       Some other considerations are,

·        Speed: the maximum speed a microcontroller can support.

·        The amount of RAM and ROM on chip

·        Power consumption: This especially critical for battery powered products.

·        The number of INPUT/ OUTPUT Ports.

·        The number of timers and counters.

·        Packaging: This is important in terms of space, assembling, and prototyping the end product.

·        How easy it is to upgrade to higher performance or lower power consumption versions.

·        Cost per unit.

·        How easy it is develop products around it.

·        Ready availability in needed quantities both now and in future.

REGISTERS: In the central processing unit , registers are used to store the information temporarily. That information could be a byte of data to be processed, or an address pointing to the data to be fetched. The vast majority of 8051 registers are 8 bit registers. In the 8051 there is only one data type:8 bits. The 8 bits of register  are from the MSB (most significant bit)D7 to the LSB(least significant bit)D0. With an 8 bit data type, any data larger than 8 bits must be broken into 8 bit chunks before it is processed.

There are a large number of registers in the 8051 some of them are discussed here.The most widely used registers of the 8051 are A (accumulator), B, R0, R1, R2, R3, R4, R5, R6, R7, DPTR (data pointer) and PC(program counter).All of the above registers are 8 bits, except DPTR and the program counter. The accumulator, register A, is used for arithmetic and logic instructions .

PROGRAM COUNTER: The important register in the 8051 is the PC (program counter). The program counter points to the address of the next instruction to be executed. As the  central processing unit fetches the opcode from the program ROM. The program counter in the 8051 is 16 bits wide. This means that the 8051 can access program addresses 0000 to ffffh, a total of  64K bytes of code.

8051 DATA TYPES AND DIRECTIVES: The 8051 microcontroller has only one data type. it is 8 bits, and the size of each register is also 8 bits. It is the job of the programmer to break down data larger than 8 bits (00 to ffh, or 0 to 255 in decimal) to be processed by the central processing unit.

ASSEMBLER DIRECTIVES:

 DB (define byte): The define byte directive is the most widely used data directive in the assembler. It is used to define the 8 bit data. When DB is used to define data, the numbers can be in decimal, binary, hex, or ASCII formats. For decimal , the “D” after  the  decimal number is optional, but using “B” (binary) and “H” (hexadecimal) for the others is required. Regardless of which is used, the assembler will convert the numbers to hex during execution.

ORG (origin): The origin directive is used to indicate the beginning of the address. The number that comes after ORG can be either in hex or in decimal. If the number is not followed by H, it is decimal and the assembler will convert it to hex.

EQU (equate): This is used to define a constant without occupying a memory location. The EQU directive does not set aside storage foe data item but associates a constant value with a data label so that when the label appears in the program, its constant value will be substituted for the label.

END directive: Another important pseudo code is the END directive. This indicates to the assembler the end of the source (asm) file. The END directive is the last line of an 8051 program, meaning that in the source code anything after the END directive is ignored by the assembler.

RTOS CONCEPT's ARM LPC2148 EMBEDDED 'C' CODES-II

PROGRAM 1:

PROGRAM TO IMPLEMENT SIMPLE SEMAPHORE

#include <RTL.h>                     

#include <LPC21xx.h>               

#include <stdio.h>

void init_serial (void);      

unsigned char msg1[]="task1\r\n", msg2[]="task2\r\n";

unsigned int i=0;

OS_TID tsk1, tsk2;

OS_SEM semaphore1;

__task void task1 (void) {

  OS_RESULT ret;

  while (1) {

    os_dly_wait(3);

    ret = os_sem_wait (semaphore1, 1);

    if (ret != OS_R_TMO) {

       while (msg1[i] != '\0')

            {

                    while (!(U0LSR & 0x20));

                    U0THR = msg1[i];

                   i++;

            }

            i=0;

          os_sem_send (semaphore1);

    }

  }

}

__task void task2 (void) {

  while (1)

  {

  

    os_sem_wait (semaphore1, 0xFFFF);

     while (msg2[i] != '\0')

            {

                    while (!(U0LSR & 0x20));

                    U0THR = msg2[i];

                   i++;

            }

            i=0;

    os_sem_send (semaphore1);

  }

}

__task void init (void) {

   init_serial ();

   os_sem_init (semaphore1, 1);

  tsk1 = os_tsk_create (task1, 10);

  tsk2 = os_tsk_create (task2, 0);

   os_tsk_delete_self ();

}

void init_serial (void) {

  PINSEL0 = 0X0000005;                 // Enable RxD0 and TxD1             

  U0LCR = 0x83;                         // 8 bits, no Parity, 1 Stop bit    

  U0DLL = 0x61;                           // 9600 Baud Rate @ 15MHz VPB Clock 

  U0LCR = 0x03;                         // DLAB = 0                         

}

int main (void) {

  init_serial();

  os_sys_init (init);

}

PROGRAM 2:

PROGRAM TO IMPLEMENT HARDWARE INTERRUPT

#include<lpc21xx.h>

#include<rtl.h>

OS_TID tsk1;

__task void job1(void);

int p=0;

void delay(unsigned int j)

{        unsigned int i;

          for(i=0;i<j;i++);

}

void extint0_isr(void)__irq

{       

unsigned int c[16]={0xF03f0200,0xF0060200,0xF05b0200,0x004f0200,0x00660200,0x006d0200,0x007d0200,0x00070200,0x007f0200,0x006f0200,0x00770200,0x007f0200,0x00390200,0x003f0200,0x00790200,0x00710200};

          unsigned int i;

          PINSEL0=0x00000000;

          IODIR0=0xF0FF0200;

          IOCLR0=0x00ff0000;

          IOSET0=c[p];

          for(i=0;i<200;i++)

          delay(10000);

          IOCLR0=0x00000200;

          p++;

          if(p>15)

          p=0;

          EXTINT|=0x00000001;

          VICVectAddr=0;

          os_evt_set(0x0001,tsk1);

          }

__task void job1(void)

{        tsk1=os_tsk_self();

     while(1)

           {   

          PINSEL1=0x00000001;

          EXTMODE=0x00000001;

          EXTPOLAR=0x00000000;

VICVectAddr0=(unsigned long)extint0_isr;

          VICVectCntl0=0x20|14;

          VICIntEnable|=0x00004000;

          delay(1000);

            }

 }

int main(void)

{          IODIR0=0xF0FF0200;

          os_sys_init(job1);

          for(;;);

}

PROGRAM 3:

PROGRAM TO INTERFACE SOFTWARE INTERRUPT

#include<RTL.H>

 #include<stdio.h>

 #include<lpc21xx.h>

 OS_TID tsk1,tsk2;

 U32 i;

 __task void job1(void);

 __task void job2(void);

 void __swi(9) ONLED (void);

 void __swi(8) OFFLED (void);

 void __SWI_8 (void)

 {

          IODIR0=0x00FF0200;

          IOSET0=0x00FF0200;

          for(i=0;i<100000;i++);

 }

 void __SWI_9 (void)

 {

          for(i=0;i<100000;i++);

          IOCLR0=0x00FF0200;

          for(i=0;i<100000;i++);

          for(i=0;i<100000;i++);

 }

 __task void job1(void)

 {

          tsk1=os_tsk_self();

          tsk2=os_tsk_create(job2,2);

          while(1)

          {

                   ONLED();

          }

 }

 __task void job2(void)

 {

          while(1)

          {

                   OFFLED();

                   os_dly_wait(1);

          }

 }

 int main(void)

 {

          os_sys_init(job1);

 }

RTOS CONCEPT's ARM LPC2148 EMBEDDED 'C' CODES-I

PROGRAM 1:

PROGRAM TO IMPLEMENT  SIMPLE TASK SWITCHING

#include <rtl.h>

#include <lpc21xx.h>

#include <stdio.h>

void init_serial (void);

OS_TID tsk1,tsk2;

char    cnt1,cnt2,test2;

__task void job1 (void);

__task void job2 (void);

char arr1[20],arr2[20];

unsigned int i = 0;

__task void job1 (void)

 {

  os_tsk_prio_self (2);

  while (1)

   {

 os_tsk_create (job2, 1);

             os_evt_wait_or (0x0001, 0x0000);

             cnt1++;

             sprintf(arr1,"counter1 :%d",cnt1);

          while (arr1[i] != '\0')

          {

                    while (!(U0LSR & 0x20));

                    U0THR = arr1[i];

                   i++;

          }

          i=0;

          while (!(U0LSR & 0x20));

          U0THR = '\r';

          if (cnt1==0x05)

          cnt1=0;

          os_dly_wait(1);                                           

    }

}

__task void job2 (void)

 {

  while (1)

   {

          cnt2++;

sprintf(arr2,"counter2 :%d",cnt2);

while (arr2[i] != '\0')

          {

                    while (!(U0LSR & 0x20));

                    U0THR = arr2[i];

                   i++;

          }

          os_dly_wait(3);

          i=0; 

          while (!(U0LSR & 0x20)); 

          U0THR = '\n';       

          if(cnt2==0x0f)

{

 cnt2=0;

os_evt_set (0x0001, tsk1);        

  }

test2=22;

           os_dly_wait(3);

          test2=0;

          os_dly_wait(3);

  }

}

int main (void)

{

cnt1=0;

cnt2=0;

   init_serial ();

  os_sys_init (job1);

  while (1);

}

void init_serial (void) {

  PINSEL0 = 0X0000005;                 // Enable RxD0 and TxD0             

  U0LCR = 0x83;                         // 8 bits, no Parity, 1 Stop bit    

  U0DLL = 0x61;                           // 9600 Baud Rate @ 15MHz VPB Clock 

  U0LCR = 0x03;                         // DLAB = 0                         

}

PROGRAM 2:

PROGRAM TO IMPLEMENT SIMPLE ROUND ROBIN TASK SWITCHING

#include <rtl.h>

#include <lpc21xx.h>

#include <stdio.h>

void init_serial (void);

int counter1;

int counter2;

char arr1[20],arr2[20];

int i=0;

__task void job1 (void);

__task void job2 (void);

__task void job1 (void) {

  os_tsk_create (job2, 0); 

  while (1) {              

    counter1++; 

          sprintf(arr1,"counter1 :%d",counter1);

          while (arr1[i] != '\0')

          {

                    while (!(U0LSR & 0x20));

                    U0THR = arr1[i];

                   i++;

          }

          i=0;

          while (!(U0LSR & 0x20));

          U0THR = '\n';

                    

  }

}

__task void job2 (void) {

  while (1) {               

    counter2++;             

sprintf(arr2,"counter2 :%d",counter2);

          while (arr2[i] != '\0')

          {

                    while (!(U0LSR & 0x20));

                    U0THR = arr2[i];

                   i++;

          }

          i=0;

          while (!(U0LSR & 0x20));

          U0THR = '\n';

  }

}

void main (void)

 {

init_serial();

  os_sys_init (job1);       

  for (;;);

}

void init_serial (void)

{

  PINSEL0 = 0X0000005;                 // Enable RxD0 and TxD0             

  U0LCR = 0x83;                         // 8 bits, no Parity, 1 Stop bit     

  U0DLL = 0x61;                           // 9600 Baud Rate @ 15MHz VPB Clock 

  U0LCR = 0x03;                         // DLAB = 0                         

}

PROGRAM 3:

PROGRAM TO IMPLEMENT  MAIL_BOX

#include <rtl.h>

#include<stdio.h>

#include<lpc214x.h>

void init_serial(void);

os_mbx_declare (MsgBox, 100);              

U32 mpool[8*sizeof(U32) ];       

unsigned int cnt1,cnt2;

char arr1[20],arr2[20];

char arr3[20]="task2deleted";

int i=0;

__task void task2 (void);

__task void task1 (void)

 {

  U32 *mptr;

  os_tsk_create (task2, 0);

  os_mbx_init (MsgBox, sizeof(MsgBox));

  mptr = _alloc_box (mpool);               

while(1)

 {

           while(!(cnt1==15))

                             {

                             cnt1++;

                             sprintf(arr1,"counter1 :%d",cnt1);

                             while (arr1[i] != '\0')

                             {        os_dly_wait(1);

                                       while (!(U0LSR & 0x20));

                                       U0THR = arr1[i];

                                      i++;

                             }

                             i=0;

                             while (!(U0LSR & 0x20));

                             U0THR = '\n';

                              os_dly_wait(5);

                             }

 if (cnt1==15)

                   {

                   mptr[0] = cnt1;

                   cnt1=0;

                   os_mbx_send (MsgBox, mptr, 0xffff); /* Send the count value to a 'Mailbox' */

                   os_dly_wait(5);

    

                    }

           }

   }

__task void task2 (void)

{

  U32 *rptr  ;

  cnt2=0;

           while(1)

           {

           os_mbx_wait (MsgBox, (void**)&rptr, 0xffff);     

         cnt2 = *rptr;    

          while(!(cnt2==30))

          {       

                             cnt2++;

                   sprintf(arr2,"counter2 :%d",cnt2);

                   os_dly_wait(2);

                             while (arr2[i] != '\0')

                             {

                             while (!(U0LSR & 0x20));

                             U0THR = arr2[i];

                             i++;

                             }

                             i=0;

                             while (!(U0LSR & 0x20));

                             U0THR = '\n';

                             os_dly_wait(5);

                      }

                    cnt2=0;

           }

           }

int main (void)

{

 init_serial();

  _init_box (mpool, sizeof(mpool), sizeof(U32));

  os_sys_init(task1);

}

void init_serial (void)

{

  PINSEL0 = 0X0000005;                 // Enable RxD0 and TxD0             

  U0LCR = 0x83;                               // 8 bits, no Parity, 1 Stop bit    

  U0DLL = 0x61;                              // 9600 Baud Rate @ 15MHz VPB Clock 

  U0LCR = 0x03;                             // DLAB = 0                         

}