ARM PROCESSOR FUNDAMENTAL

The arm core has functional units such as ALU, Address registers, Register file, Barrel shifter, MAC and instruction decoder. All these functional blocks are connected by data buses.

DATA enters the processor core through the data bus. The data may be an instruction to be executed or a data item. Basically, ARM core follows Von Neumann implementation of the ARM in which the data items and instructions share the same bus. In contrast, Harvard implementations of the ARM use two separate buses, one of the data items and other for the instructions.

Instruction decoder translates the instruction into the binary form (executable form) before they are executed. Each instruction executed belongs to a particular instruction set.

The ARM processor uses load-store architecture. This means it has two, instruction types for transferring data in and out of the processor.  They are LOAD and STORE.

LOAD instructions copy data from memory to register in the core, and conversely the STORE instruction copy data from register to memory. These are no data processing instructions that directly manipulate data in memory. Thus data processing is carried out solely in registers. Data items are placed in the register file called as storage bank made up of 32-bit registers. Since the ARM core is 32-bit processor, most instructions treat the registers as holding signed or unsigned 32-bit values. The sign extend hardware converts signed 8-bit and 16-bit numbers to 32-bit values as they read from memory and placed in a register.

ARM instruction typically have two source registers i.e, Rn and Rm, and a single result or destination register, Rd. Source operands are read from the register file using the internal buses A and B, respectively. The ALU (arithmetic logic unit) takes the register values Rn and Rm from the A and B buses and computes a result. Data processing instructions write the result in Rd directly to the register file. Load and Store instruction use the ALU to generate an address to be held in the address register and broadcast on the Address bus.

One important feature of the ARM is that register Rm alternatively can be p reprocessed in the barrel shifter before it enters the ALU. Together the Barrel shifter and ALU can calculate a wide range of expressions and address. After passing through the functional units, the result in Rd is written back to the register  file using the Result bus. For load and store instructions the increment-er updates the address register before the core reads or writes the next register value from or to the next sequential

Memory location .The processor continues executing instruction until an exception or interrupt changes the normal execution flow.