ARM PROCESSOR MODES

The access rights of the processor mode are done in the Current Program Status Register (CPSR) itself. The processor mode is used to determine which registers are active. Each processor mode is either privileged mode or non privileged : A privileged mode allows the full read-write access to the CPSR. Conversely, A non privileged mode still allows read access to the control field in the CPSR but still allows read-write access to the conditional fields. 

There are seven processor modes in total. Out of which six are privileged modes and one is non privileged mode(user). The six privileged modes are Abort mode; Fast interrupt mode, Interrupt request mode, Supervisor mode, System mode, and Undefined mode. The processor enters the abort mode when there is a failed attempt to access memory. Fast interrupt request and Interrupt request modes correspond to the two interrupt levels available on the ARM processor. Supervisor mode is the mode that the processor   is in after the reset and is generally the mode that an operating system kernel operates in. System mode is a special version of user mode that allows full read-write access to the CPSR. Undefined mode is used when the processor encounters an instruction that is undefined or not supported by the implementation. User mode is used for programs and applications.

There are 37 registers in register file. Out of which, 20 registers are hidden from a program at different times. These registers are called banked registers.  These banked registers are available only when the processor, is in a particular mode. The registers of particular mode are denoted by an underline character post-fixed to the mode mnemonics or _mode. For example, banked registers r13_abt, r14_abt and spsr_abt are available only when the processor is in abort mode.

Every processor mode expect user mode can change mode by writing directly to the mode bits of the CPSR. All processor modes except system mode have a set of associated banked register that are a subset of the main 16 registers. A banked register maps one-to-one onto a user mode register. If the processor mode is changed, a banked register from the new mode will replace an existing register.

For example, when the processor is in the interrupt request mode, the instruction you execute still access registers named r13 and r14. However, these registers are the banked registers r13_irq and r14_irq. The user mode registers r13_usr and r14_usr are not affected by the instruction referencing these registers. A program still has normal access to other registers r0 to r12.

The processor mode can be changed by a program that writes directly to the CPSR only if the processor core has to be in privileged mode or by hardware when the core responds to an exception or interrupt.